Error Floor Analysis of LDPC Column Layered Decoders

In this letter, we analyze the error floor of column layered decoders, also known as shuffled for low-density parity-check (LDPC) codes under saturating sum-product algorithm (SPA). To estimate floor, evaluate failure rate different trapping sets (TSs) that contribute to frame in region. For each such TS, model dynamics SPA vicinity TS by a linear state-space incorporates information message-passing schedule. Consequently, parameters and change result order which messages layers are updated. This, turn, causes code function scheduling. Based on proposed analysis, then devise an efficient search find schedule minimizes floor. Simulation results presented verify accuracy estimation technique.